Pawan Kumar Upadhyaya
17+ years of experience in IP Verification and Verification IP Development • DDR IP Verification (System Verilog – UVM) • PCIe Gen-5... | Noida, Noida, India
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Pawan Kumar Upadhyaya’s Emails pu****@ca****.com
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Pawan Kumar Upadhyaya’s Location Noida, Noida, India
Pawan Kumar Upadhyaya’s Expertise 17+ years of experience in IP Verification and Verification IP Development • DDR IP Verification (System Verilog – UVM) • PCIe Gen-5 IP Transaction Layer Module Level Verification (System Verilog – UVM) • PCIe Gen-4 IP Verification (DemoTB) (System Verilog – UVM) • Ethernet IP & Subsystem Level Verification (System Verilog – UVM) • Ethernet Verification IP Development (System Verilog – UVM) • LIN Verification IP Development (System Verilog – UVM) • JTAG Verification IP Development (System Verilog – UVM) • Ethernet Verification IP development in Ethernet R&D Team and ownership of following Ethernet interfaces. This also include a PSUI (PureSpec User Interface) which supports a System Verilog (SV) Layer on top of the e-core to cater SV Users including UVM & OVM. 1) MII (Media Independent Interface) 2) RMII (Reduced Media Independent Interface) 3) SMII (Serial Media Independent Interface) 4) GMII (Gigabit Media Independent Interface) 5) RGMII (Reduced Gigabit Media Independent Interface) 6) TBI (Ten Bit Interface) 7) RTBI (Reduced Ten Bit Interface) 8) SGMII (Serial Gigabit Media Independent Interface) 9) QSGMII (Quad Serial Gigabit Media Independent Interface) 10) 1000Base-KX 11) XGMII(Extended Gigabit Media Independent Interface) 12) XAUI (Extended Attachment Unit Interface) 13) RXAUI (Reduced Extended Attachment Unit Interface) 14) 10GBaser-KX4 15) XSBI (Extended Sixteen Bit Interface) 16) 10GBase-KR 17) 20GBase-R 18) 25/50G Interfaces 19) XLGMII (40 Gbps) 20) CGMII (100 Gbps) 21) 40GBase-KR4, 40GBase-CR4 22) 100GBase-KR10, 100GBase-CR10, 100GBase-KR4, 100Gbase-CR4 23) MDIO 24) ISO/OSI Model’s Upper Layer Frame Generation and Extraction Architecture for IPv4/IPv6, TCP/UDP, MPLS, SNAP, PTP, FC Layer Packets. • CPSW_3G(Common Platform Ethernet Switch - 3G) RTL Verification using Specman(e Language) • CPSW_3GF(Common Platform Ethernet Switch - 3GF) RTL Verification using Specman(e Language) • USB 3.0 eVC Development (Specman - e Language - eRM Compliant) • USB 2.0 eVC Development(Specman - e Language - eRM Compliant) • USB 2.0 RTL Verification using Specman(e Language) • Module Level Verification of PDP Logic Board using Specman(e Language) • AES RTL Design in Verilog HDL & its Verification using Specman(e Language)
Pawan Kumar Upadhyaya’s Current Industry Cadence Design Systems
Pawan
Kumar Upadhyaya’s Prior Industry
Tata Elxsi
|
Quantum Think Technologies
|
Cadence Design Systems
|
Synopsys
|
Broadcom
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Work Experience
Cadence Design Systems
Sr. Principal Design Engineer
Fri Mar 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Broadcom
R&D Engineer IC Design 5 (Principal Engineer)
Sat Sep 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Feb 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
R&D Engineer, Sr II
Sat Aug 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Aug 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Cadence Design Systems
Member of Consulting Staff
Tue Jul 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Cadence Design Systems
Senior Member of Technical Staff
Sun Jul 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jun 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Cadence Design Systems
Member of Technical Staff
Sun Aug 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jun 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Quantum Think Technologies
IC Design Engineer
Tue Sep 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jul 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Tata Elxsi
Engineer
Sun Apr 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Aug 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Pawan Kumar Upadhyaya Email Addresses
FAQ About Pawan Kumar Upadhyaya
-
Pawan Kumar Upadhyaya is located at
Noida, Noida, India -
Pawan Kumar Upadhyaya is a
17+ years of experience in IP Verification and Verification IP Development • DDR IP Verification (System Verilog – UVM) • PCIe Gen-5 IP Transaction Layer Module Level Verification (System Verilog – UVM) • PCIe Gen-4 IP Verification (DemoTB) (System Verilog – UVM) • Ethernet IP & Subsystem Level Verification (System Verilog – UVM) • Ethernet Verification IP Development (System Verilog – UVM) • LIN Verification IP Development (System Verilog – UVM) • JTAG Verification IP Development (System Verilog – UVM) • Ethernet Verification IP development in Ethernet R&D Team and ownership of following Ethernet interfaces. This also include a PSUI (PureSpec User Interface) which supports a System Verilog (SV) Layer on top of the e-core to cater SV Users including UVM & OVM. 1) MII (Media Independent Interface) 2) RMII (Reduced Media Independent Interface) 3) SMII (Serial Media Independent Interface) 4) GMII (Gigabit Media Independent Interface) 5) RGMII (Reduced Gigabit Media Independent Interface) 6) TBI (Ten Bit Interface) 7) RTBI (Reduced Ten Bit Interface) 8) SGMII (Serial Gigabit Media Independent Interface) 9) QSGMII (Quad Serial Gigabit Media Independent Interface) 10) 1000Base-KX 11) XGMII(Extended Gigabit Media Independent Interface) 12) XAUI (Extended Attachment Unit Interface) 13) RXAUI (Reduced Extended Attachment Unit Interface) 14) 10GBaser-KX4 15) XSBI (Extended Sixteen Bit Interface) 16) 10GBase-KR 17) 20GBase-R 18) 25/50G Interfaces 19) XLGMII (40 Gbps) 20) CGMII (100 Gbps) 21) 40GBase-KR4, 40GBase-CR4 22) 100GBase-KR10, 100GBase-CR10, 100GBase-KR4, 100Gbase-CR4 23) MDIO 24) ISO/OSI Model’s Upper Layer Frame Generation and Extraction Architecture for IPv4/IPv6, TCP/UDP, MPLS, SNAP, PTP, FC Layer Packets. • CPSW_3G(Common Platform Ethernet Switch - 3G) RTL Verification using Specman(e Language) • CPSW_3GF(Common Platform Ethernet Switch - 3GF) RTL Verification using Specman(e Language) • USB 3.0 eVC Development (Specman - e Language - eRM Compliant) • USB 2.0 eVC Development(Specman - e Language - eRM Compliant) • USB 2.0 RTL Verification using Specman(e Language) • Module Level Verification of PDP Logic Board using Specman(e Language) • AES RTL Design in Verilog HDL & its Verification using Specman(e Language) Cadence Design Systems -
Pawan Kumar Upadhyaya currently works in the
Cadence Design Systems -
Pawan Kumar Upadhyaya specializes in
17+ years of experience in IP Verification and Verification IP Development • DDR IP Verification (System Verilog – UVM) • PCIe Gen-5 IP Transaction Layer Module Level Verification (System Verilog – UVM) • PCIe Gen-4 IP Verification (DemoTB) (System Verilog – UVM) • Ethernet IP & Subsystem Level Verification (System Verilog – UVM) • Ethernet Verification IP Development (System Verilog – UVM) • LIN Verification IP Development (System Verilog – UVM) • JTAG Verification IP Development (System Verilog – UVM) • Ethernet Verification IP development in Ethernet R&D Team and ownership of following Ethernet interfaces. This also include a PSUI (PureSpec User Interface) which supports a System Verilog (SV) Layer on top of the e-core to cater SV Users including UVM & OVM. 1) MII (Media Independent Interface) 2) RMII (Reduced Media Independent Interface) 3) SMII (Serial Media Independent Interface) 4) GMII (Gigabit Media Independent Interface) 5) RGMII (Reduced Gigabit Media Independent Interface) 6) TBI (Ten Bit Interface) 7) RTBI (Reduced Ten Bit Interface) 8) SGMII (Serial Gigabit Media Independent Interface) 9) QSGMII (Quad Serial Gigabit Media Independent Interface) 10) 1000Base-KX 11) XGMII(Extended Gigabit Media Independent Interface) 12) XAUI (Extended Attachment Unit Interface) 13) RXAUI (Reduced Extended Attachment Unit Interface) 14) 10GBaser-KX4 15) XSBI (Extended Sixteen Bit Interface) 16) 10GBase-KR 17) 20GBase-R 18) 25/50G Interfaces 19) XLGMII (40 Gbps) 20) CGMII (100 Gbps) 21) 40GBase-KR4, 40GBase-CR4 22) 100GBase-KR10, 100GBase-CR10, 100GBase-KR4, 100Gbase-CR4 23) MDIO 24) ISO/OSI Model’s Upper Layer Frame Generation and Extraction Architecture for IPv4/IPv6, TCP/UDP, MPLS, SNAP, PTP, FC Layer Packets. • CPSW_3G(Common Platform Ethernet Switch - 3G) RTL Verification using Specman(e Language) • CPSW_3GF(Common Platform Ethernet Switch - 3GF) RTL Verification using Specman(e Language) • USB 3.0 eVC Development (Specman - e Language - eRM Compliant) • USB 2.0 eVC Development(Specman - e Language - eRM Compliant) • USB 2.0 RTL Verification using Specman(e Language) • Module Level Verification of PDP Logic Board using Specman(e Language) • AES RTL Design in Verilog HDL & its Verification using Specman(e Language) -
Pawan Kumar Upadhyaya speaks the following languages:
No languages available. -
Pawan Kumar Upadhyaya has prior experience in the following industries:
Broadcom , Synopsys , Cadence Design Systems , Cadence Design Systems , Cadence Design Systems , Quantum Think Technologies , Tata Elxsi -
Pawan Kumar Upadhyaya has the following professional experience:
Cadence Design Systems , Broadcom , Synopsys , Cadence Design Systems , Cadence Design Systems , Cadence Design Systems , Quantum Think Technologies , Tata Elxsi . -
You can view Pawan Kumar Upadhyaya’s
LinkedIn profile at LinkedIn URL. -
Pawan Kumar Upadhyaya’s work email addresses are
[email protected] . -
Pawan Kumar Upadhyaya works at
Cadence Design Systems
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